Current Issue : October - December Volume : 2019 Issue Number : 4 Articles : 5 Articles
A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si\nheterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less\ntunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively\nuse the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase\nthe electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to\nimprove the gate-to-channel control. In addition, the effects of Ge content, electrode work functions,\nand device structure parameters on the performance of H-DLTFET are researched in detail, and\nthen the above optimal device structure parameters can be obtained. Compared to the DLTFET, the\nsimulation results show that the maximum on-state current, trans-conductance, and output current of\nH-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by\ntwo orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same\ntime, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and\n0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the\nultra-low power integrated circuits....
An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-\nOxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ)\ndevices are added on top of a conventional D flip-flop for temporary storage during the power-down.\nAn area overhead of the temporary storage is minimized by reusing a part of the D flip-flop\nand an energy overhead is reduced by a current-reuse technique. In addition, two optimization\nstrategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design\nphase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for\nreducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model\ntargeting an implementation in a 10 nm technology node. Results indicate that area overhead is\n6.9% normalized to the conventional flip flop. Compared to the best previously known NVFFs,\nthe proposed circuit succeeded in reducing the area by 4.1* and the energy by 1.5*. The proposed\nplacement strategy of the NVFF shows an improvement of nearly a factor of 2-18 in terms of area\nand energy, and the pulse duration modulation provides a further energy reduction depending on\nfault tolerance of programs....
Power MOSFETs specially designed for space power systems are expected to\nsimultaneously meet the requirements of electrical performance and radiation hardness. Radiationhardened\n(rad-hard) power MOSFET design can be achieved via cell structure optimization. This\npaper conducts an investigation of the cell geometrical parameters with major impacts on radiation\nhardness, and a rad-hard power MOSFET is designed and fabricated. The experimental results\nvalidate the devicesâ?? total ionizing dose (TID) and single event effects (SEE) hardness to suitably\nsatisfy most space power system requirements while maintaining acceptable electrical performance....
This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with\na resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS)\ntechnology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase\ndelay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase\nLocked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and\nvariations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms\nof the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of\n2.2 MGy SiO2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity\n(DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively....
This paper presents a comprehensive investigation on the self-sustained oscillation of\nsilicon carbide (SiC) MOSFETs. At first, based on the double pulse switching test, it is identified\nthat the self-sustained oscillation of SiC MOSFETs can be triggered by two distinct test conditions.\nTo investigate the oscillatory criteria of the two types of self-sustained oscillation, a small-signal ac\nmodel is introduced to obtain the transfer function of the oscillatory system. The instability of the\noscillation is thereby determined by the two conjugate pole pairs of the transfer function. By analyzing\nthe damping ratios of the two pole pairs, the parametric sensitivity of various circuit and deviceâ??s\nparameters on the two types of self-sustained oscillation are obtained. The analyses reveal the\noscillatory criteria of the self-sustained oscillation for SiC MOSFETs. Based on the oscillatory criteria,\nnecessary methods are proposed to prevent the oscillation. The proposed oscillation suppression\nmethods are validated by the experiment at the end of the paper....
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